An application specific integrated circuit (ASIC) is typically generated on a silicon wafer having a plurality of etchings for transmitting electrical signals and other chemical elements, such as Gallium Arsenide etched thereon for providing electrical functionality, such as transistors. In a typical assembly process, a plurality of integrated circuits are formed on a single wafer and portions of the wafer are tested to determine temperature, supply voltage and process variations. In a typical system, process variations are measured once during the production test of the ASIC and a speed grade is assigned to the individual integrated circuits. The temperature is measured in the system in which the integrated circuit is operating and the result is, in some designs, used for controlling a clock frequency. Moreover, voltage can be measured and the results used, by some designs, to control clock frequency.
The above-noted solutions treat the process variations, supply voltage and temperature measurements separately, and thereupon try to combine them on a system level. This solution may not lead to an optimal characterization of the performance characteristics of a specific integrated circuit due to relative intrinsic values, such as temperature dependency of multiple integrated circuits based on the number of process variations and differences in supply voltages.
Furthermore, when a plurality of integrated circuits are generated on a single wafer, the division of the individual integrated circuits from the wafer is typically performed by a cutting process. A binning operation is performed, wherein integrated circuits having specific performance levels are provided to specific corresponding bins. For example, if a fabricated wafer containing a plurality of integrated circuits contains integrated circuits having performance speeds within ten different ranges, the binning process consists of sorting and disbursing the integrated circuits into ten separate categories. The above-noted prior art performance determination process does not allow for binning of the specific integrated circuits, based on general testing and due to the reduction in the amount of die space in current fabricated integrated circuits.
As such, there exists a need for a method and apparatus that allows for determining a processing speed of an integrated circuit, wherein the integrated circuit may be on a wafer having a plurality of integrated circuits, wherein the performance speed is determined independent of process, voltage and temperature measurements and may be based on the execution of a system application on the integrated circuit. Moreover, there also exists a need for determination of processing speeds for integrated circuits of the plurality of integrated circuits to improve the binning process.